The invention relates to a phase lock loop, and more specifically to a phase lock loop capable of adjusting states automatically and control method thereof.
FIG. 1A is a block diagram of a conventional phase lock loop (PLL), having a phase/frequency detector (PFD) 90, a charge pump 92, a voltage-controlled oscillator (VCO) 94, and a frequency divider 96. The PFD 90 detects the transitional edges of the feedback clock Clkfb and the reference clock Clkref to generate comparative signals UP and DN which, in turn, charge and discharge the charge pump 92 to generate a control voltage Vc. The VCO 94 generates an output clock Clkvco of variable frequency in response to the control voltage Vc. The frequency divider 96 divides the frequency of the clock Clkvco to generate the feedback clock Clkfb.
VCO is generally designed to operate in a single state, having a single voltage frequency transfer curve. There are two types of VCOs in terms of the voltage-frequency transfer curve slope, high gain and low gain VCOs. FIG. 1B shows two voltage-frequency transfer curves A and B, corresponding to high gain and low gain VCOs respectively. As depicted, high gain VCO provides the advantage of broader tuning frequency range. The performance of the output clock stability in high gain VCO, however, is inferior since frequency of the output clock is susceptible to the change in control voltage Vc. Conversely, low gain VCO provides a more stable frequency of the output clock but a narrower tuning frequency range. As a result, selecting a suitable voltage-frequency transfer curve for a VCO has been important for circuit designers.